An application for xe2x80x9cESD Protection for Open drain I/O Pad in Integrated Circuits with Parasitic Field FET Devicexe2x80x9d, Ser. No. 09/664,420, assigned to the assignee of this invention, has a related disclosure.
This invention relates generally to semiconductor integrated circuit devices and more specifically to a circuit device with improved protection against electrostatic discharge (ESD) stress at the input-output pad of the device.
ESD voltages are a familiar problem for developers of semiconductor chips for integrated circuit devices. An ESD voltage appears at an input-output pad of the chip when, for example, a voltage is picked up by a conductor that runs between the pad and a circuit node external to the device. A pad is a small conductive area on a chip that forms a circuit node where external conductors can be attached to the chip. On the chip, a pad is usually connected to the input of an input buffer circuit or to the output of a driver circuit or to both. The driver itself can provide protection against some ESD events, as will be discussed later.
One familiar driver circuit is an inverter formed by two FETs. An upper FET is connected to conduct between the output pad and Vdd and a lower FET is connected to conduct between the output pad and Vss. (Vss and Vdd are the usual designations for the power supply terminals of the device.) In one binary state of an input signal, the gates of the FETs receive voltages that turn off the lower FET and turn on the upper FET to pull the output pad up. In the other binary input state, the signals at the gates of the FETs turn off the upper FET and turn on the lower FET to pull the output pad down.
An ESD protection device clamps the ESD voltage to a value that will not damage circuits on the chip that are connected to the pad. An ESD protection device creates a low resistance current path that clamps the voltage at the pad to a safe value. Sometimes a resistor is connected in one or more of the branches between the pad and the protected circuits to further isolate the pad voltage from the protected circuits.
An ESD current path can be established when a semiconductor junction breaks down in response to a high ESD voltage. This junction breakdown occurs because the voltage on the ESD side of the junction has reached a break down value with respect to the voltage on the other side of the junction. The voltage on the other side of the junction is commonly established by the power supply nodes, Vss and Vdd, and the ESD current path ordinarily includes Vss or Vdd. The ESD current can also flow in a path between Vss and Vdd.
The driver circuit that has just been described can be used for ESD protection. When a high positive voltage appears at the pad with respect to the grounded Vss, the drain to substrate junction of the lower FET is reverse biased and it breaks down at a predetermined voltage. Thus, in response to a high positive voltage, the lower FET conducts to Vss and clamps the pad voltage to a value that does not damage other circuits connected to the pad. Similarly, when a high negative voltage appears at the pad with respect to the grounded Vss, the lower FET conducts to Vss and limits the pad voltage. Commonly, the drain is made larger to handle the ESD current. The larger drain increases the capacitance at the pad and in this way slows the rise and fall of pulses at the pad.
Sometimes an open drain driver is used with an input-output pad. This driver circuit is like the circuit just described except that it does not have the upper FET: the output is pulled down in the way described but it is pulled up by the external circuits that are connected to the pad, and these circuits do not provide a low resistance path for an ESD current from the pad to Vdd.
The high ESD voltage at a pad can be referenced to either Vss or Vdd, and the pad must be protected against both forms of the ESD voltage. It will be helpful to consider an example of a circuit that does not meet this object: an open drain driver. As already explained, an open drain driver would maintain a low voltage between the pad and Vss. However, in a circuit with an open drain driver for ESD protection, a high voltage could is develop between the pad and Vdd.
The prior art has suggested connecting FET between Vss and Vdd to turn on and conduct in series with the open drain driver when an ESD voltage appears between the Pad and Vdd. The Vss to Vdd FET has its source connected to Vss, its drain connected to Vdd, and its gate connected to Vss to keep it turned off in normal operation. When an ESD voltage of either polarity appears between the pad and Vdd, the drain to channel junction or the source to channel junction (depending on the polarity of the ESD voltage) of the Vss to Vdd FET breaks down and conducts in series with the driver to conduct the ESD current between the pad and Vdd.
One object of this invention is to provide improved ESD protection, particularly for a pad having an open drain driver circuit.
We provide a conductive path between Vss and Vdd that becomes enabled in response to a high voltage that would otherwise develop between these power supply points during some ESD events. The device comprises FET connected between Vss and Vdd. The gate of the FET is connected to ground to keep it turned off during operations when only normal voltages appear at the pad.
The preferred FET is formed as two parallel FETs having a common drain diffusion and individual source diffusions. A frame of the opposite conductivity type as the drain and source surrounds the two FETs. This circuit forms a cell, and a driver is made up of an array of these cells. The array can be made in any convenient size, and in the driver that will be described later the number of rows and columns is dependent on the device dimensions of the FET in the open drain driver.
A cell can also form a Vss to Vdd FET that turns on in response to an ESD voltage between the pad and Vdd. The driver conducts between the pad and Vss and the Vss to Vdd FET conducts between the pad and Vdd, and these two FETs thereby form a circuit between the pad and Vdd. To reduce the occupied silicon area, a merged layout structure is described in this specification.
It will be helpful to visualize the driver and the pad as each having a square or rectangular shape. (The actual shape may be different.) The driver is located with one of its edges closely adjacent to an edge of an associated pad. This location provides a low resistance in the ESD current path, and the low resistance reduces the voltage drop that would otherwise be produced by the flow of the ESD current at the pad.
The Vss to Vdd FET can be formed in several configurations. When it is a single cell, it can be located along any of the edges of the driver that do not abut the pad. This configuration keeps a low resistance between the pad and the Vss to Vdd FET but allows the driver to have the position of lowest possible resistance. When two Vss to Vdd FETs are located along opposite edges of the driver, their resistance is paralleled.
Several configurations are disclosed that provide this advantageous spatial relation between the pad, the driver and the Vss to Vdd FET. In some configurations, the Vss to Vdd FET is formed as an array of cells that are extensions of the rows or columns of the driver. In one configuration, a single Vss to Vdd FET is located between the drivers of two pads and is shared by the two pads with a merged layout structure.
Other features of the invention will appear in the description of my preferred embodiment.